الحوسبة الكوانتية و تطبيقاتها

Abstract

Reversible logic has received a great attention in the recent years due to its ability to reduce the power dissipation. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. The arithmetic logic unit (ALU) is an important part of central processing unit (CPU) as the execution unit. This thesis presents a complete design of a new (reversible/quantum) arithmetic logic unit (ALU) that can be part of a programmable reversible computing device such as a quantum computer. The proposed ALU based on a reversible low power control unit and small performance parameters full adder named double Peres gates. The presented QALU can produce the largest number of arithmetic and logic functions (28) and have the smallest number of quantum cost and delay compared with existing designs