Abstract:
Transistors made of thin layers (Thin Film Transistor: TFT) are used primarily for the realization of active matrix flat panel displays liquid crystal. They constitute the basic element of a specific part of electronic known as “Large Surface Electronic”.
The Poly-TFTs are made of a thin un-doped polycrystalline silicon film deposited on a glass substrate by the Low Pressure Chemical Vapor Deposition technique LPCVD; this choice limits the technological process to the temperature < 600°C. The benefit of pc-Si is to make devices with large grain size. Unfortunately, according to the conditions during deposition, the pc-Si layers can consist of a random superposition of grains of different sizes, where it appears grains boundaries parallels and perpendiculars.
In this paper, the transfer characteristics IDS-VGS are simulated by solving a set of two-dimensional (2D) drift-diffusion equations together with the usual density of states (DOS: exponential band tails and Gaussian distribution of dangling bonds) localized at the grains boundaries. The effect of density of intergranular and interface traps states, band to band tunneling (BBT), thickness of active layer, grain size and position of grain boundaries on the TFT's characteristics for a drain bias equal to 1V have been investigated
