Contribution à l’étude du transport électrique à travers des oxydes très minces (<10nm) dans des structures MOS

Abstract

The continuous down-scaling of MOS transistors dimensions over the last years allowed a significant revolution in the semiconductor industry. However, in order to maintain this trend, shrinking of conventional n MOS dimensions is no more sufficient enough and replacement of some transistor materials is one of the alternative ways currently under study to solve this issue. In this context, the work presented here, on the study of the transport properties of the nMOS architectures combining both new technology options; a high-k gate dielectric in place of the SiO2 and a biaxialy tensile strained channel. Firstly, the influence of biaxial tensile strain on the electrical properties of the n-MOS transistor has been investigated using a numerical solution of drift diffusion partial equations. The simulation results showed a significant improvement in electrons mobility and an increase in current ID (VD). Then, we study the impact of the incorporation of a high-k gate stack on improving leakage through the oxide. The calculation results obtained from the ATLAS (SILVACOTCAD) simulator have shown that the use of high dielectric constant oxides significantly reduces the tunneling leakage current through increased physical thickness of the stack. However, we noted a decrease of the electron mobility in the channel If MOS transistors with a high-k dielectric HfO2 hafnium relative to SiO2 Finally, the feasibility and interest to introduce a strained silicon channel to counteract the degradation of mobility associated with stacking metal / HfO2 are then discussed.